1. Field of the Invention
This invention relates to a method and circuit for detection of failures in the solder-joint networks in digital electronic packages such as Field Programmable Gate Arrays (FPGAs) and Microcontrollers and between the package's ball grid array (BGA) and printed wire boards (PWBs).
2. Description of the Related Art
Solder-joint connections from digital electronic packages such as FPGAs or Microcontrollers to Printed Wire Boards (PWB) are a major reliability problem. Modern Ball Grid Array (BGA) packages have several thousand pins and the number of pins on these packages is likely to increase over the next several years. The increased number of pins on the packages is necessary to support the evolving complexity of circuits; however, one of the drawbacks of the increase is reduced reliability. For many applications it would be useful to detect failures or precursors to failures in mechanical connections that lie inside the digital logic on the die, through the multiple mechanical connections and solder-joint connections between the die and package and through the external solder-joint connections to circuitry on the PWB; together the “solder joint network”.
As shown in FIG. 1, an exemplary FPGA 10 includes at least one flip-chip 12 consisting of a die mount 18 and die 16 mounted inside a cavity 14 of a BGA package 22. Electrical components such as transistors, diodes and capacitors that are configured via mechanical connections such as aluminum or copper traces or tungsten vias on a die 16 together constitute the FPGA. The FPGA includes write logic that is connected through an output buffer to a pad on the die. Similarly an input buffer is connected from a pad to read logic. Flip-chip 12 is placed inside BGA package 22 so that the solder balls 20 (also called solder bumps) inside the BGA package 22 touch pads, lands or vias of flip-chip 12 and they are soldered to form solder-joint connections. Vias lead from contacts (not shown) of solder bumps 20 to an outside ball limiting metallurgy (BLM) 24 and primary BGA solder balls 26 to complete the FPGA 10. The FPGA is placed so that primary BGA solder balls 26 contact solder paste on metal LANDs 28 on a PWB 30. The assembled PWB is heated and the solder balls 26 and solder paste melt and reflow to attach themselves to the metal LAND. The PWB is configured so that the metal LANDs are connected by vias and/or wiring 32 to one or more I/O nodes 34 for external circuitry on the PWB.
As shown in FIG. 2, the integrity of the external solder joint can be evaluated by measuring the bump connection resistance of a BGA package 40 flip-chip mounted to a PWB 41 during a test and judging defects by the degree of change in the connection resistance. Wire segments 42 connect vias 43 inside the package and PWB wiring 44 connects pads 45 on the PWB to connect solder bumps 46 attached to ball-limiting metallurgy 47 from the primary BGA in a “daisy chain”. A meter 48 directly measures the resistance for all bumps 46 at the same time by either applying a voltage and measuring a current or vice-versa. The meter is typically a large, heavy and expensive piece of test equipment that applies well-regulated (low noise) voltages, unlike the actually power supplies on operational packages. Alternately, the wire segments and PWB can be configured to measure the resistance between two bumps 46 at a time, so increases in resistance due to cracking can be monitored.
The techniques for direct measurement of the solder-joint resistance have a number of limitations. The BGA package and PWB are ‘blanks’ or ‘dummies’ configured for a 4-wire or 2-wire continuous measurement, and therefore the test packages are not the same as the operational devices. Specifically, the package does not include the FPGA flip-chip containing the operational logic gates and buffers. It follows that these tests cannot be performed on actual operational devices, either in the lab or particularly in the field, and can not be monitored 24-7. Finally, although there are several instruments available to perform these measurements, besides being bulky and suitable for lab testing, these instruments cannot be used to perform real-time, in-use testing of fielded, operational FPGA BCA solder joint networks.